Chameleon
Chameleon is the industry’s most powerful low-power Forward Error Correction (FEC) ASIC. Manufactured on Altera’s HardCopy II platform, Chameleon implements TrellisWare’s Flexible Low Density Parity Check (F-LDPC) technology, the world’s most flexible FEC solution. Designed to meet the demands of modern communications and storage systems, TrellisWare’s F-LDPC offers a wide range of code rates and block sizes, reconfiguration on the fly, and the ability to achieve Gbps throughputs – all without compromising performance at any operating point. Chameleon supports 40 code rates, 8 standard block sizes and virtually any digital modulation type. Additional block sizes can be supported using an external PROM. Modulation, block size and code rate can be changed on the fly on a block by block basis, allowing Chameleon to support ARQ systems with variable throughput requirements based on link quality such as microwave point-to-point links, storage systems, satellite modems and robust military communications.
The figure below illustrates how Chameleon meets the very different and diverse requirements of various applications.
Click to enlarge imageKey Features
- Early stopping for reduced power or increased throughput
- Simple single-ended LVCMOS interfaces
- Fully pipelined parallel interface for block to block full programmability
- Standard SPI slave interface for programming constants to reduce board interconnects
- Programmable number of I/Q channels to allow trade-offs between throughput and board interconnect
- Handshaking signals to allow data flow control with both upstream and downstream resources
- Independent core and interface clocks for flexibility
TrellisWare built the beyond 1 Gbps Chameleon ASIC based on our F-LDPC technology to address a wide range of applications with a flexible, powerful, low cost solution.
Related Materials
- Chameleon Product Brochure
(326KB PDF) - F-LDPC Product Brochure
(546KB PDF) - F-LDPC Whitepaper
(2MB PDF)