Standard & Custom
TrellisWare offers a wide range of highly efficient custom- and standards-based decoder cores utilizing all types of advanced codes. Decoder cores for Low Density Parity Check (LDPC) codes, Serially Concatenated Convolutional Codes (SCCC) and Parallel Concatenated Convolutional Codes (PCCC) are available. An example of an available PCCC core designed and built by TrellisWare is shown below:
Click to enlarge imageIn designing standard FEC cores, we build on our coding and core design expertise to reduce development time and core size. This approach provides faster time-to-market and lower silicon costs for our customers.
HomePlug AV Turbo Convolutional Code
HomePlug products connect consumer devices such as HDTVs, media centers, set-top boxes and home theater components located in different rooms through the power lines in a home. Transmitting data at more than 100 Mbps over home power lines is extraordinarily challenging due to the limited bandwidth and noise environments found on various home power lines. Powerful FEC technology is required to achieve the desired data rates at the target error rates. Turbo convolutional codes (TCCs) were selected by the industry as the FEC technology for HomePlug AV. However, TCCs have significant decoder complexity and high encoder and decoder latencies. TrellisWare addresses these issues by drawing on our many years of TCC design experience to produce HomePlug AV TCC cores with minimal complexity and latency. We help our customers reduce their silicon cost due to our lower complexity, and get to market much faster due to the maturity of our product.
Key features of TrellisWare’s HomePlug AV TCC offering include:
- HomePlug AV-compliant TCC encoder and decoder
- Supports PB16, PB136 and PB520 frame sizes
- Supports rate 1/2 and rate 16/21 code rates
- Includes channel interleaver and deinterleaver
- Programmable number of decoder iterations
- Encoder and decoder programmable on the fly
- Encoder throughput of 300 Mbps (150 MHz clock)
- Decoder throughput of 135 Mbps (4 iterations, 150 MHz clock)
- Encoder latency of 4181 cycles (PB520)
- Tail-biting can be disabled to halve encoder latency
- Decoder latency of 574 cycles per sub-iteration (PB520)
- Encoder complexity of 13 Kgates, with 30 Kbits of memory
- Decoder complexity of 122 Kgates, with 162 Kbits of memory
- Single clock domain
- Successfully synthesized at 150 MHz with UMC L130 library (faster clock is certainly possible)
- FPGA cores also available
More information:
In addition to the HomePlug TCC core, TrellisWare is currently developing encoder/decoder products for the DVB-S2, 802.11n and 802.16e LDPC codes. Using our low complexity decoding architectures, we aim to provide significant savings in silicon cost and/or higher throughputs for our customers.
Contact us with your specific FEC requirements
TrellisWare's HomePlug TCC core's bandwidth efficiency is seen for all three modes of operation.
Related Materials
- HomePlug Product Brochure
(240KB PDF)