Forward Error Correction Technologies

Turbo codes and related advanced/modern codes (e.g., serial/parallel concatenated convolutional codes, LDPC codes, and turbo product codes) offer outstanding coding gains compared to traditional FEC approaches — greater than 3-4 dB in many cases. On the down side, one feature lacking from these new codes is flexibility. Their outstanding performance is usually only achieved for a limited range of code rates, block sizes or modulation types; operation outside this limited range results in degraded performance or significantly increased complexity. Another issue is the difficulty in achieving high-data throughputs with modern code decoders compared to decoders for more traditional FEC schemes, such as Reed-Solomon.

Higher Performance Modern FEC Designs

TrellisWare has developed a family of flexible turbo-like codes that achieve superior performance across a wide range of code rates, block sizes and modulation types, even at high-data throughputs. Our F-LDPC and Flexicode products are compatible with low-complexity decoder architectures that are well suited to very high throughput decoders, and provide great performance at lower complexity than other turbo-like codes.

The figure below shows the block diagram of the F-LDPC encoder. TrellisWare’s patented F-LDPC techniques employ systematic codes. The outer code is a 2-state rate ½ non-recursive convolutional code, and the inner code is a 2-state rate 1 recursive convolutional code. The use of 2-state constituent codes means the decoder complexity of the F-LDPC is very low.

The use of the Single Parity Check (SPC) means that different code rates can be achieved by only varying J (the number of bits input to the SPC). This makes the F-LDPC very flexible in achieving any code rate of interest. As far as the block sizes are concerned, the only thing that changes from one block size to another is the interleaver (I). Any good algorithmic interleaver can be used, which provides F-LDPC block-size flexibility down to bit level. These simple parameter changes can be made “on the fly”, giving flexibility from block to block, if desired.

This very simple F-LDPC structure allows low-complexity decoder implementations for very high throughputs. TrellisWare demonstrated a 1+Gbps implementation of the F-LDPC in FPGAs at MILCOM 2006. Please click here for more information.

Flexible FEC Extracts Maximum Performance

The flexibility of TrellisWare’s codes helps our customers in three major ways:

Keeping system overhead to a minimum, which facilitates the highest possible throughput at a given signal-to-noise ratio.
Allowing for major system changes — such as modulation types, code rates and block sizes — at any time during product development process, without the worry of having to change the decoder core/ASIC, which provides insurance against unforeseen modifications.
Supporting designs which must change rapidly as the channel or media or desired message type changes. For example, system protocol messages may be much smaller than data messages with which they are interspersed and a different level of coding on each message type may be desired. With TrellisWare’s flexibility you can accommodate both with a simple parameter change, on the fly.

The figure below show the significant overhead gains achievable by using the F-LDPC over a fixed block-size/code rate code. While a fixed block-size/code rate system operates at a pre-determined operating SNR, regardless of how much SNR is available, a system using the F-LDPC has the capability of adjusting its operating SNR, so it only uses the required amount of overhead.

In the top figure, the area between the SNR curve and the operating SNR represents the wasted (un-needed) overall coding overhead applied in the system using a fixed block size/code rate. The operating SNR must accommodate the worst expected available SNR, which results in excessive overhead usage and hence lost throughput. In the case of the F-LDPC (bottom figure), the overhead to code for a given SNR can be made as small as necessary.

Another way to look at this is by studying the area under the operating SNR line, which is a measure of the throughput the system can achieve. In the top figure, the throughput is fixed for all time, with the same amount of information sent regardless of available SNR. In the case of the F-LDPC (bottom figure), the throughput varies since there is more available SNR, allowing for much more information to be sent during a fixed time period.

Better FEC Enables Better Decoders

TrellisWare has also made innovations in the area of decoder implementation for modern codes. We have developed a superior implementation architecture that enables throughputs 10 to 100 times greater than those available today, using strong modern codes that don’t sacrifice performance.

TrellisWare can supply ASIC and FPGA decoders for the F-LDPC and FlexiCode tailored to specific applications, including higher throughputs, lower complexity, better threshold performance, lower floors, and greater flexibility. We also have extensive experience in the design and implementation of modern codes and traditional FEC. Our decoder architectures can be applied to many standard modern codes as well. We can assist with the design of the optimal FEC solution for any application, and rapidly implement decoders for any code.

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Related Materials

F-LDPC Whitepaper
(2MB PDF)