Flexible Low Density Parity Check (F-LDPC) FEC

Download F-LDPC Spec Sheet

TrellisWare’s Flexible Low Density Parity Check (F-LDPC) code family meets the demand for high performance forward error correction solutions. F-LDPC offers code rates and modulations without sacrificing decoder latency or throughput. F-LDPC is available as encoder and decoder cores for FPGA and ASIC implementations. Standard cores support 8 block sizes, 40 code rates, and 4 modulation types, and they are configurable on the fly. F-LDPC is deployed in very-small-aperture terminal (VSAT) systems, free space optical (FSO) communication systems, holographic storage systems, a number of military waveforms, and TrellisWare’s own tactical MANET products.

Features

Unparalleled Flexibility

  • Single encoder/decoder core supports any block size, code rate, and modulation combination
  • Configurable on the fly: Block to block changes with zero latency
  • Custom block sizes and code rates can be added to standard cores

Unparalleled Performance

  • Capacity-approaching performance across all supported rates
  • Low error floors
  • High performance for small block sizes

High-Throughput, Low-Complexity

  • Up to 10 Gbps throughput in a single FPGA
  • 100 Gpbs+ throughputs achievable in ASICs
  • Complexity lower than competing LDPC and turbo codes

Standard Products

TrellisWare’s off-the-shelf F-LDPC cores support

  • 40 codes rates (1/2–32/33)
  • 8 block sizes (128, 256, 512, …, 16384 bits)
  • 4 modulations (BPSK, QPSK, 8PSK, 16QAM)
  • Log likelihood ratio (LLR) inputs for other digital modulations

Standard cores are delivered within weeks of purchase. Customize with different block sizes and rates before or after delivery.  

Standard Package for F-LDPC includes

  • Encoder core (synthesized netlist targeted to chosen FPGA)
  • Decoder core (synthesized netlist targeted to chosen FPGA)
  • Datasheets for encoder and decoder cores
  • Modelsim simulation library
  • Test bench and test vectors
  • A bit-true C simulation library – called from MATLAB