Modern Forward Error Correction
F-LDPC FEC
A highly flexible FEC solution offering universally good performance, high speed decoding, and low implementation complexity.
F-LDPC FEC Licensing
TrellisWare provides intellectual property (IP) products. Most prevalent are the Flexible-Low Density Parity Check (F-LDPC) Forward Error Correction (FEC) cores incorporated into many commercial and government waveforms.
FEC is the spell checker of digital communications and corrects errors in received data. Modern FEC’s like TrellisWare’s F-LDPC are robust and have performance close to the theoretical optimum. F-LDPC is essential to error-free communications.
The F-LDPC is deployed in very small aperture terminal (VSAT) systems, free space optics (FSO) communication systems, holographic storage systems, a number of military waveforms, and TrellisWare’s own TSM™ products.
The F-LDPC FEC is part of TrellisWare’s technology base that is essential to waveform and signal processing elements.
Features
Unparalleled Flexibility
- Single encoder/decoder core supports 40 code rates (1/2–32/33) and multiple block sizes. Default block sizes are 128, 256, 512, …, 16384 bits
- Single encoder/decoder core supports any block size, code rate, and modulation combination
- Configurable on the fly: Block to block changes with zero latency
- Custom block sizes and code rates can be added to standard cores
Proven Performance
- Capacity approaching performance with low implementation complexity; maximizes Message Completion Rates (MCR)
- Low error floors
- High performance for small block sizes
High-Throughput, Low-Complexity
- Up to 10 Gbps throughput in a single FPGA
- 100 Gbps+ throughputs achievable in ASICs
- Complexity lower than competing LDPC and turbo codes
Product Deliverables
F-LDPC Core Support
- 40 codes rates (1/2–32/33)
- 8 block sizes (128, 256, 512, …, 16384 bits)
- 4 modulations (BPSK, QPSK, 8PSK, 16QAM)
- Log likelihood ratio (LLR) inputs for other digital modulations
Standard cores are delivered within weeks of purchase. Customize with different block sizes and rates before or after delivery.
Standard Packages
- Encoder core (Synthesized netlist targeted to chosen FPGA)
- Decoder core (Synthesized netlist targeted to chosen FPGA)
- Datasheets for encoder and decoder cores
- Modelsim simulation library
- Test bench and test vectors
- A bit-true C simulation library – called from MATLAB
All F-LDPC FEC product deliverables come as software/firmware files.
Want to improve your communications?
Contact TrellisWare for more information about F-LDPC FEC licensing.